Conventionally, an information processing device that conducts pipeline processing (referred to below as “pipeline processing device”) is known in which one instruction is divided into plural stages, processing of each stage is sequentially executed per set processing timing and processing of mutually different stages is concurrently executed at the same processing timing, whereby the plural instructions (instruction processing cycles comprising the plural stages) are processed in parallel to obtain an instruction result per processing timing (e.g., see David A. Patterson and John L. Hennessy, Computer Organization & Design, Second Edition, Nikkei Business Publications, Inc., 1999).
Here, as one example of this type of pipeline processing device, a CPU that conducts 5-stage pipeline processing by dividing one instruction into five stages comprising instruction fetch (IF), instruction decode (DEC), execute (EXE), memory access (MA) and write-back (WB) will be described using FIGS. 4 and 5.
FIG. 4 is a block diagram showing the configuration of a data path portion in the CPU, and FIG. 5 is a timing diagram for describing an operation when the CPU has received an interrupt request.
The CPU is one where an instruction is read from a memory (mainly a ROM) at the IF stage, the instruction read at the IF stage is decoded and a register is read at the DEC stage, and arithmetical and logical computation is conducted in response to the content of the instruction decoded at the DEC stage and an address of the instruction to be read by the IF stage and an address when accessing the memory are computed at the EXE stage. Moreover, the memory is accessed (i.e., data is read or written) at the MA stage using, as the address, the result of the computation at the EXE stage, and the result of the computation at the EXE stage or the data read from the memory at the MA stage is stored in an internal register at the WB stage.
As shown in FIG. 4, a CPU 101 is disposed with pipeline registers 102 to 104 that store data necessary at each stage, control information and the execution results of each stage.
Of these, the pipeline register 102 temporarily retains, as input data of the DEC stage, the instruction read at the IF stage. Below, the pipeline register 102 will be referred to as the IF/DEC buffer 102. The pipeline register 103 temporarily retains, as input data of the EXE stage, data necessary for computation at the EXE stage on the basis of the result of decoding at the DEC stage. Below, the pipeline register 103 will be referred to as the DEC/EXE buffer 103. Moreover, the pipeline register 104 temporarily retains, as input data of the MA stage, the result of the computation at the EXE stage. Below, the pipeline register 104 will be referred to as the EXE/MA buffer 104.
The CPU 101 is also disposed with a register file 105 comprising plural registers that store data loaded from the memory at the MA stage; a computing unit 106 that executes, on the basis of data prepared in the DEC/EXE buffer 103 at the DEC stage, arithmetical and logical computation and computation of an address of an instruction to be read at the IF stage and addresses when accessing the memory, i.e., processing of the EXE stages; and a program counter 107 for designating the address in which is stored the instruction to be read at the IF stage.
Moreover, the CPU 101 is also disposed with a multiplexer 108 that selects any of output from the register file 105, a ROM address (referred to below as “setting address”) in which is stored information relating to a header address of an interrupt processing routine (referred to below as “interrupt address information”) or data loaded from an external memory via a data bus 30 and provides this to the DEC/EXE buffer 103; a multiplexer 110 that selects any of output of the computing unit 106 and updated output where the output of the program counter 107 is counted up and renders this into input data of the program counter 107; a multiplexer 111 that selects any of output from the program counter 107 and output from the EXE/MA buffer 104 and outputs this to an address bus 20; and a multiplexer 112 that selects any of output from the EXE/MA buffer 104 and data loaded via the data bus 30 and supplies this to the register file 105.
It should be noted that, in addition to the above-described data path portion, the CPU 101 is also disposed with a control unit (not shown) that decodes the instruction fetched at the IF stage on the basis of data stored in the IF/DEC buffer 102 and, in accordance with the decoding result thereof, executes processing that reads data necessary for computation from the register file 105 and executes processing that switches the settings of the multiplexers 108 and 110 to 112.
The CPU 101 configured in this manner normally executes processing in the following sequence.
First, at the IF stage, an instruction is read from the address set by the program counter 107 and the instruction is stored in the IF/DEC buffer 102.
Next, at the DEC stage, decoding of the instruction stored in the IF/DEC buffer 102 is conducted and, in accordance with the decoding result thereof, data necessary at the EXE stage is prepared from within the register file 105 and the data is stored in the DEC/EXE buffer 103.
Next, at the EXE stage, the data prepared at the DEC stage is stored in the DEC/EXE buffer 103 and, on the basis of the stored data, the computing unit 106 executes computation designated in accordance with the result of the decoding at the DEC stage.
Next, at the MA stage, the result of the computation by the computing unit 106 is stored in the EXE/MA buffer 104 or the program counter 107. Then, in a case where the data is an address for memory access, the data stored in the EXE/MA buffer 104 is outputted to the address bus via the multiplexer 111. In a case other than this, the data stored in the EXE/MA buffer 104 is supplied in the register file 105 via the multiplexer 112.
Next, at the WB stage, the data stored in the EXE/MA buffer 104 or the data loaded from the address designed by that data is stored in the register file 105.
Thereafter, the processing of each stage is repeatedly executed in parallel.
Incidentally, numerous peripheral circuits are normally internally disposed in the microcomputer disposed with the CPU 101, and the interrupt processing routine must be executed in correspondence to interrupt requests from these peripheral circuits.
An operation when an interrupt processing routine corresponding to an interrupt request is started when an interrupt request has been received in this manner will be described using FIGS. 4 and 5.
As shown in FIG. 5, assuming that an interrupt request has been received at a stage starting at a processing timing t2, the multiplexer 108 immediately switches to a setting that supplies the setting address to the DEC/EXE buffer 103 in lieu of data supplied from the register file 105.
Thus, at the DEC stage of an instruction processing cycle C1, the instruction fetched at the IF stage of a processing timing t1, i.e., the instruction that is being stored in the IF/DEC buffer 102 at that point in time is nullified, and the setting address is transmitted to the EXE stage (DEC/EXE buffer 103) in lieu of the decoding result of the instruction.
Next, at a processing timing t3, the setting address is stored in the DEC/EXE buffer 103, and the computing unit 106 is set to allow the setting address stored in the DEC/EXE buffer 103 to pass without changing the value (specifically, zero may be added to the setting address or the logical product of the setting address and the data, all of whose bits are 1, may be determined).
Thus, at the EXE stage of the instruction processing cycle C1, the setting address is transmitted as is to the MA stage (EXE/MA buffer 104).
Next, at a processing timing t4, the setting address is stored in the EXE/MA buffer 104, the multiplexer 111 is set to output the output of the EXE/MA buffer 104 to the address bus 20, and the multiplexer 108 is set to supply, to the DEC/EXE buffer 103, the data loaded from the setting address of the memory via the data bus 30.
Thus, at the MA stage of the instruction processing cycle C1, memory access to the setting address is executed, and the data loaded thereby, i.e., the interrupt address information is stored in the DEC/EXE buffer 103.
In other words, the interrupt address information loaded at the MA stage of the instruction processing cycle C1 is bypassed to the DEC stage of an instruction processing cycle C3.
Next, at a processing timing t5, the interrupt address information is stored in the DEC/EXE buffer 103, the computing unit 106 is set to determine the header address of the interrupt processing routine on the basis of the interrupt address information stored in the DEC/EXE buffer, and the multiplexer 110 is set to supply the output of the computing unit 106 to the program counter 107 instead of the updated output of the program counter 107.
Thus, at the EXE stage of the instruction processing cycle C3, the header address of the interrupt processing routine is determined and this header address is supplied to the program counter 107.
Next, at a processing timing t6, the computation result (header address) of the computing unit 106 is stored in the program counter 107, the multiplexer 111 is set to output the output of the program counter 107 to the address bus 20, and the data (instruction) loaded from the header address via the data bus 30 is stored in the IF/DEC buffer 102.
Thus, the header address of the interrupt processing routine is set in the program counter 107 by the MA stage of the instruction processing cycle C3, and fetching of the instruction immediately begins in accordance with the setting value of the program counter 107.
In other words, the interrupt processing routine corresponding to the interrupt request received at the DEC stage beginning at the processing timing t2 begins at the IF stage beginning at the processing timing t6.
In this manner, the startup time required from the reception of the interrupt request to when the interrupt processing routine actually starts (here, the time corresponding to four stages from t2 to t6) is the time at which the processing to be executed is interrupted, and it is preferable to shorten this time as much as possible. In particular, with respect to microcomputers for controlling embedded devices where rapid accommodation with respect to interrupt requests is necessary, there are many microcomputers where the processing itself to be implemented with respect to the interrupt requests simply ends in a short time, but the interrupt requests arise frequently. In other words, the time consumed in order to start the interrupt processing routine occupies a large part of the entire processing, and the length of the startup time thereof ends up exerting a large affect on the processing capacity of the microcomputer.